DesignCon is the yearly Conference for all things SI, and was held at the Santa Clara Convention Center in January 2016. In addition to serving on the Technical Program Committee and hosting DesignCon’s yearly AMI Panel, SiGuys also presented the sessions below and received a Best Paper Nomination. Scroll down for pictures from the show.
- Best Paper Award Finalist: “Building IBIS-AMI Models from Datasheet Specifications” paper and slides (Intel co-author)
Some high-speed SerDes devices do not come with IBIS-AMI models. For situation when an AMI model is not available, this paper describes a process for building IBIS-AMI models using SerDes datasheet information and lab measurements. The process is illustrated using a case study of a PCIe Gen3 8Gbps SerDes device. A series of stress test and eye scans are used to fine-tune and correlate model to actual hardware. Attend this presentation to understand how to build an IBIS-AMI model for any high-speed SerDes that may lack one.
Large systems with longer product lifecycles provide performance tuning opportunities such as SerDes setting optimizations and manufacturing improvements. This paper describes newly-developed techniques for equalization tuning and discontinuity reduction, offering additional design margin. Cost reductions are also achieved as Signal Integrity (SI) analysis demonstrates performance parity removing non-essential re-timers and PCBs layers. This is the fourth in a series of DesignCon papers detailing the design and implementation of a system characterized by multiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps).
- AMI Panel Discussion: “Accurate AMI Analysis – Whose Responsibility Is It?” slides (Avago, SiSoft, Cisco, Intel, Keysight, IBM Panelists)
With AMI models and analyses tools increasingly relied upon for critical design decisions, it’s important that the industry as a whole collaborate to ensure the accuracy of such analysis. This panel creates a framework for that discussion, and demonstrates that every engineer regardless of their current job function has a role to play. This panel combines industry experts who focus on this challenge every day, giving them unique insight into what is required for improvement. Join us as we partner across company boundaries, examine the issues and propose solutions.
- “A SerDes Balancing Act: Co-Optimizing Tx and Rx Settings to Maximize Margin” slides and webinar (Si-Soft co-author)
Increasing complexity in SerDes Tx and Rx designs requires carefully balancing Tx and Rx equalization to truly optimize serial link performance. “Co-Optimizing” a link refers to intelligently and simultaneously trading off all Tx and Rx equalization factors in light of a channel’s passive behavior to maximize eye margin at the receiver’s sampling latch. The DesignCon 2016 paper “New SI Techniques for Large System Performance Tuning”(Jan 20, 11:05AM) presents a case study of how Co-Optimization was used to achieve 60% better performance on 25% longer links. This session expands on that study to dig deeper into the mechanics involved in co-optimizing an even wider spectrum of links. Links dominated by length, ISI, or a combination of both, as well as industry-standard and hypothetical channels are examined. Optimal performance is achieved by knowing when and how to trade-off factors such as ISI and amplitude, and knowing which types of equalization to apply at the Tx and/or Rx. Performance gains are achieved through firmware settings without any changes to hardware. Results presented are based on SiSoft’s OptimEye technology, which makes advanced Co-Optimization accessible to anyone working with serial links.
Pictures: SiGuys at DesignCon 2016