Signal Integrity in Practice
A LIVE 2-Day Workshop where Hardware and SI EEs learn how to succeed at Gen2 SI – hands on!
Featuring: Donald Telian, SI Consultant, Pioneer, and Author
Upcoming Classes: Silicon Valley (Milpitas) CA – May 14/15 2025
Join us as we simplify SI, removing the mystery, learning proven, straightforward processes.
About the SI Masterclass
This class empowers attendees to achieve Signal Integrity, in Practice. Combining classroom instruction, hands-on labs, software, and ‘back-at-your-desk’ office hours, the class ensures successful application of SI skills. Attendees are now using this proven multi-dimensional approach on their current projects (for example, PCIe Gen5/6 systems).
Over 90% of attendees surveyed rate the class’s instructor and multi-dimensional approach
‘EXCEPTIONAL’
Focusing on Gen2 SI while building upon Gen1 givens, attendees learn the skills necessary to solve SI both NOW and in the decades ahead. Day 1 covers delivering signals cleanly through the (passive) PCB system before Day 2 adds the (active) IC capabilities. Active SerDes equalization (EQ) radically changes how SI is achieved and practiced, and this class shows you how.
Though higher data rates do require updated design practices, “doubling data rate isn’t something to be afraid of, it’s simply what we do,” says your instructor, Donald Telian, who has doubled data rate more than a dozen times throughout his 40-year career. Telian simplifies the challenge by sharing what’s necessary, and what isn’t. Register now to attend a class near you. We’ll see you there!
Who Should Attend
- Hardware EEs, wanting to expand their skill set to include SI
- SI Engineers, interested in learning from an SI pioneer and industry veteran
- Engineering Managers, desiring understanding and language for today’s design process
Prerequisites: basic understanding of Gen1 SI can be helpful, yet not required.
About the Instructor: Donald Telian
Donald Telian is a Signal Integrity Consultant and the Owner of SiGuys. He celebrates four decades of SI pioneering with the publication of his new book Signal Integrity, In Practice and its associated LIVE 2-day class. Consulting since the beginning of the serial link technology revolution, Donald consistently helps customers migrate to next-generation data rates again and again. With tens of thousands of serial links in production spanning all types of electronic standards and products, he simplifies SI by sharing what’s necessary and what isn’t. Telian is widely known as the SI designer of the PCI bus, the originator of IBIS modeling, and has taught SI techniques to thousands of engineers in more than 15 countries.
Masterclass Agenda
DAY 1 – PASSIVE SYSTEM SI
Today’s systems must deliver signals through passive interconnect with 10 mV accuracy, requiring loss and discontinuities to be carefully understood and managed. Day 1 explains how to correctly combine PCBs, connectors, cables, vias, traces, packages etc., to ensure a meaningful signal arrives at the Rx. Hands on labs ensure an intuitive understanding of passive impedances and loss. Attendees finish Day 1 with a sense of “I can do this,” regardless of how mysterious and complex SI seemed at the start of the day.
8:00 Continental Breakfast & The SI Hangout
9:00 Gen2 SI & Serial Link Dominance
9:30 The Primary Gen2 SI Failures are NOT What You Think
10:30 Understanding and Fixing Discontinuities
11:30 Lab 1: Feature Impedances & Discontinuities
12:00 Catered Lunch
1:00 Hardware SI: Budgeting and Managing Loss
1:30 Lab 2: Eyes, Loss, Gbps & BERs
2:00 Yikes I’ve Got Stubs, & Route/Stackup/Fab Secret Sauce
3:30 Software SI: Equalization Registers and Firmware
4:00 Day 1 Wrapped
4:30 5k Run (optional)
6:00 Hosted Class Dinner
DAY 2 – ADDING THE ICs
Integrity of signals cannot be achieved without factoring in the ICs, particularly integrated equalization (EQ). Because EQ is the number one reason links both work and fail, Day 2’s hands-on labs quickly boot up attendees on how to configure it effectively. Day 2 also takes a deeper look at topics such as crosstalk, stackups, and DDRx, with a practical focus on what automation (e.g., design tools, measurements, link training) will handle and what it will not. Day 2 rounds out the class with cutting-edge, unique, and engaging topics.
8:00 Continental Breakfast, SI Hangout, Day 1 Aha’s
9:00 EQ Types, Pros/Cons, Impact on Eyes and Pulse Response
10:30 Lab 3: Deploying EQ Elements in a System
11:00 Pulse Response and Eyes/EQ – how to optimize/fix links
12:00 Catered Lunch
1:00 Lab 4: Open Your Eyes Using EQ – pulse response secrets
2:00 Class Competition (friendly style)
2:30 Jitter, Standards, Measurements, DDRx
3:00 Stackups, SI & Layout, Report Templates, Cheat Sheets
3:30 Signal Integrity Futures – Where do we go from here?
4:00 Day 2 Wrapped, Experiment/Complete Labs, SI Hangout
5:00 Class is Done – time to go rock your designs!
WHAT’S INCLUDED:
- 2-Day LIVE Workshop with all course materials
- A free 30-day MATLAB® license, including SI and RF PCB Toolboxes
- Hard-back copy of Donald Telian’s book Signal Integrity, in Practice
- 2 months of Office Hours with Donald Telian
- Telian’s proven SI Report templates and cheat sheets
- All Meals included, including a group dinner out after day one
- Optional participation in 5K run, with associated prizes
- Sponsor/vendor fair during Day 2 lunch
- Most importantly a memorable, fun, and engaging learning experience!
Not Included: Travel, accommodation, and ground transportation
Videos & Photos
Class Partners
Masterclass Locations
Silicon Valley (Milpitas) CA, May 14-15, 2025
Rohde & Schwarz
490 N McCarthy Blvd #100
Milpitas, CA 95035