Published Works


DesignCon Full-day SI Course:  Pragmatic Signal Integrity

DesignCon AMI Panel:  “IBIS-AMI: New Users, New Uses”  (Cadence, Cisco, GlobalFoundries, Intel, SiSoft)


DesignCon Boot Camp Training:  Pragmatic Signal Integrity

DesignCon AMI Panel:  Getting the Most from IBIS-AMI: Tips & Secrets from the Experts (IBM, SiSoft, Cisco, Broadcom, Cadence, Brocade – pic)


PCB Design Magazine’s July 2016 Signal Integrity Issue:  “New SI Techniques” (PDF version)

SPI Italy:  “7 Challenging SI/PI Problems That Have NO Existing Solution

European IBIS Summit:  “Using IBIS-AMI Models to Maximize Performance Given SerDes EQ and Channel ISI & Loss”  (SiSoft co-author)

DesignCon Paper: “New SI Techniques for Large System Performance Tuning” (SiSoft co-authors)

DesignCon Paper: “Building Accurate IBIS-AMI Models from Datasheets and Lab Measurement” (Intel co-author)

DesignCon AMI Panel: “Accurate AMI Analysis – Whose Responsibility Is It?” (with Avago, Cisco, IBM, Intel, Keysight, SiSoft)

Industry Webinar:  “A SerDes Balancing Act: Co-Optimizing Tx and Rx Equalization Settings to Maximize Margin” (SiSoft co-author)

Video Interview on Signal Integrity

Tips for PCB Designers – video

EDN Article:  Accurate AMI Analysis – Whose Responsibility Is It?


DesignCon AMI Panel: “Can we use AMI analysis to predict meaningful BERs?” (with Avago, Cisco, Ericsson, IBM, Intel, Keysight, SiSoft)


DesignCon Best Paper Award: “Moving Higher Data Rate Serial Links into Production – Issues & Solutions” (Ericsson & SiSoft co-authors)


DesignCon Paper: “Fast, efficient, and accurate: via models that correlate to 20 GHz” and slides (SiSoft co-authors)


DesignCon Paper: “Simulating Large Systems with Thousands of Serial Links” and slides (Ericsson & SiSoft co-authors)

DesignCon Tutorial: “Channel Eye Diagram Generation, Pre-Hardware” Session 2-MP2


DesignCon Paper Award Finalist: “Simulation Techniques for 6+ Gbps Serial Links” also slides and audio (Ericsson & Amphenol co-authors)


Webinar: “Advanced Techniques for Channel Analysis” and slides (Cadence Allegro PCB SI GXL specific)

DesignCon Paper Award: “New Serial Link Simulation Process, 6 Gbps SAS Case Study” and presentation (Hitachi GST & IBM co-authors)

XrossTalk Magazine: “A Process for Serial Link Signal Integrity Analysis”


CDNLive MVP:  “New Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study” and presentation (Hitachi GST & IBM co-authors)


Article:  “Signals on Serial Links: Now you see ‘em, now you don’t.”

EETimes:  “Soaring data rates signal coming crisis”

CDNLive:  “Using Allegro PCB SI GXL (630) to make your Multi-GHz Serial Link work right out of the box” and presentation

CDNLive:  “Adapting Signal Integrity Tools and Techniques for 6 Gbps and Beyond”


DesignCon:  “New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links” and presentation (Intel co-authors)IBIS Summit:  “Modeling Complex IO with IBIS 4.1”

EETimes:  “IBIS can help model gigabit pre-emphasis”

Webinar:  “New IBIS Techniques for Modeling Complex IO”


FPGA Journal:  “Fast and Accurate Multi-GigaHertz Modeling Techniques”

Paper:  “S-Parameter Correlation of typical PCB interconnect structures” shorter version at CommsDesign (co-written with Intel)

Webinar: “Introducing Channel Analysis for PCB Systems”

Webinar:  “Understanding and Using S-Parameters for PCB Signal Integrity”

Webinar:  “How to Build Fast and Accurate Multi-Gigabit Transceiver Models”


Xcell Journal:  “Surf the Serial Wave to Success”


ICUG:  “Optimizing your Design Chain with Design Kits – Practical Advice for Kit Builders and Kit Users”

ProgWorld:  “Implementing Muilti-Gigabit Serial Links in a System of PCBs” and video

Xcell Journal:  “Get up to Multi-Gigabit Speed” (Xilinx co-author)


Design Solutions: “Definition and Description of High-Speed Design Process”


IBIS Summit:  “Behavioral Receiver Modeling”


Article:  “Definition of High-Speed”


DesignCon:  “An Optimized Methodology for High-Speed Design” (co-written with Intel)


DesignCon Best Paper:  “Signal Integrity Engineering in High-Speed Digital Systems” and in Chinese


EDN:  “Treat pc-board traces as transmission lines to specify drive buffers”

IBIS:  “Telian founds IBIS Open Forum” (scroll to first meeting, bottom of page)


Video: “PCI: Second Decade Performance”


US Patent:  “5,028,809 Computer Bus Structure Permitting Replacement of Modules During Operation” (HP co-authors)