Published Works
2024
Telian’s Posts about Gen2 SI on LinkedIn
Altium’s OnTrack YouTube: Modern vs. Old School Signal Integrity
Telian’s New SI Masterclass Videos: 3-min intro, 29-min detail
Robert Feranec’s YouTube: Fix Diff-pairs Using Software, and more
EEcosystem YouTube: Free SI Cheat Sheet for Hardware Engineers
2023
SI Journal: Discontinuity Proximity Effect, DPE (and simulation files)
Advanced Signal Integrity Forum Keynote: “S + I = $, How to Succeed at a Career in Signal Integrity” (webinar, slides)
DesignCon Paper Award Finalist: “Managing Differential Via Crosstalk and Ground Via Placement for 40+ Gbps Signaling” (MathWorks, GigaTest Labs, and Xconn Technologies co-authors, and slides and pic)
DesignCon Paper: “PCIe Gen5 (25+ Gbps) Signal Integrity Implementation – Issues & Solutions” (Xconn Technologies co-authors, and slides)
Telian presents at IBIS Open Forum’s 30-year Celebration: Press Release, slides and pics 1 & 2
2022
Donald Telian’s Book: “Signal Integrity, In Practice” available for purchase on Amazon
Signal Integrity Journal: Numerous articles on SI by Donald Telian
Eric Bogatin Podcast: An Interview with Donald Telian
EDIcon: “Signal Integrity Cheat Sheet – Data-Rate Driven Design Decisions”
DesignCon Best Paper: “Proper Ground Return Via Placement for 40+ Gbps Signaling” (MathWorks co-authors)
Signal Integrity, In Practice: References section from Book
DesignCon AMI Panel: “AMI Models and the Seven-Year Itch” (Cadence, Intel, MathWorks, Micron, Serialink Systems, photo)
2020
DesignCon AMI Panel: “Succeeding with Next-Generation AMI Models & Analysis” (Cadence, Intel, MathWorks, Micron, Cisco – pic1, pic2)
2019
DesignCon AMI Panel: “Which Model When? Succeeding with IBIS-AMI” (Cadence, Intel, MathWorks, Micron – picture)
2018
DesignCon Full-day SI Course: Pragmatic Signal Integrity
DesignCon AMI Panel: “IBIS-AMI: New Users, New Uses” (Cadence, Cisco, GlobalFoundries, Intel, SiSoft)
2017
DesignCon Boot Camp Training: Pragmatic Signal Integrity
DesignCon AMI Panel: Getting the Most from IBIS-AMI: Tips & Secrets from the Experts (IBM, SiSoft, Cisco, Broadcom, Cadence, Brocade – pic)
2016
PCB Design Magazine’s July 2016 Signal Integrity Issue: “New SI Techniques” (PDF version)
SPI Italy: “7 Challenging SI/PI Problems That Have NO Existing Solution”
European IBIS Summit: “Using IBIS-AMI Models to Maximize Performance Given SerDes EQ and Channel ISI & Loss” (SiSoft co-author)
DesignCon Paper: “New SI Techniques for Large System Performance Tuning” (SiSoft co-authors)
DesignCon Paper: “Building Accurate IBIS-AMI Models from Datasheets and Lab Measurement” (Intel co-author)
DesignCon AMI Panel: “Accurate AMI Analysis – Whose Responsibility Is It?” (with Avago, Cisco, IBM, Intel, Keysight, SiSoft)
Industry Webinar: “A SerDes Balancing Act: Co-Optimizing Tx and Rx Equalization Settings to Maximize Margin” and Audio MP3 (SiSoft co-author)
Video Interview on Signal Integrity
EDN Article: Accurate AMI Analysis – Whose Responsibility Is It?
2015
DesignCon AMI Panel: “Can we use AMI analysis to predict meaningful BERs?” (with Avago, Cisco, Ericsson, IBM, Intel, Keysight, SiSoft)
2014
DesignCon Best Paper Award: “Moving Higher Data Rate Serial Links into Production – Issues & Solutions” (Ericsson & SiSoft co-authors)
2013
DesignCon Paper: “Fast, efficient, and accurate: via models that correlate to 20 GHz” and slides (SiSoft co-authors)
2012
DesignCon Paper: “Simulating Large Systems with Thousands of Serial Links” and slides (Ericsson & SiSoft co-authors)
DesignCon Tutorial: “Channel Eye Diagram Generation, Pre-Hardware” Session 2-MP2
Understanding TDR (written by Mike Steinberger)
2010
DesignCon Paper Award Finalist: “Simulation Techniques for 6+ Gbps Serial Links” also slides and audio (Ericsson & Amphenol co-authors)
2009
Webinar: “Advanced Techniques for Channel Analysis” and slides (Cadence Allegro PCB SI GXL specific)
DesignCon Paper Award: “New Serial Link Simulation Process, 6 Gbps SAS Case Study” and presentation (Hitachi GST & IBM co-authors)
XrossTalk Magazine: “A Process for Serial Link Signal Integrity Analysis”
2008
CDNLive MVP: “New Technologies for 6 Gbps Serial Link Design & Simulation, a Case Study” and presentation (Hitachi GST & IBM co-authors)
2007
Article: “Signals on Serial Links: Now you see ‘em, now you don’t.”
EETimes: “Soaring data rates signal coming crisis”
CDNLive: “Using Allegro PCB SI GXL (630) to make your Multi-GHz Serial Link work right out of the box” and presentation
CDNLive: “Adapting Signal Integrity Tools and Techniques for 6 Gbps and Beyond”
2005
DesignCon: “New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links” and presentation (Intel co-authors)
IBIS Summit: “Modeling Complex IO with IBIS 4.1”
EETimes: “IBIS can help model gigabit pre-emphasis”
Webinar: “New IBIS Techniques for Modeling Complex IO”
2004
FPGA Journal: “Fast and Accurate Multi-GigaHertz Modeling Techniques”
Paper: “S-Parameter Correlation of typical PCB interconnect structures” shorter version at CommsDesign (co-written with Intel)
Webinar: “Introducing Channel Analysis for PCB Systems”
Webinar: “Understanding and Using S-Parameters for PCB Signal Integrity”
Webinar: “How to Build Fast and Accurate Multi-Gigabit Transceiver Models”
2003
Xcell Journal: “Surf the Serial Wave to Success”
2002
ICUG: “Optimizing your Design Chain with Design Kits – Practical Advice for Kit Builders and Kit Users”
ProgWorld: “Implementing Muilti-Gigabit Serial Links in a System of PCBs” and video
Xcell Journal: “Get up to Multi-Gigabit Speed” (Xilinx co-author)
2001
Design Solutions: “Definition and Description of High-Speed Design Process”
2000
IBIS Summit: “Behavioral Receiver Modeling”
1999
Article: “Definition of High-Speed”
1998
DesignCon: “An Optimized Methodology for High-Speed Design” (co-written with Intel)
1997
DesignCon Best Paper: “Signal Integrity Engineering in High-Speed Digital Systems” original proceedings and in Chinese
1993
EDN: “Treat pc-board traces as transmission lines to specify drive buffers”
IBIS: “Telian founds IBIS Open Forum”
1992
Video: “PCI: Second Decade Performance”
1991
US Patent: “5,028,809 Computer Bus Structure Permitting Replacement of Modules During Operation” (HP co-authors)